1. Field of the Invention
The present invention relates to a semiconductor manufacturing process, and in particular to a method for manufacturing an N-type thin-film transistor (TFT).
2. The Related Arts
Flat panel display devices have various advantages, such as thin device body, low power consumption, and being free of radiation and have a wide range of application. Flat panel display devices that are currently available generally include liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).
A thin-film transistor (TFT), which is an important constituent component of the flat panel display devices, can be formed on a glass substrate or a plastic substrate to serve as a switching device and a driving device involved in display devices, such as LCDs and OLEDs.
Based on the carrier that forms an electric current in an TFT, TFTs can be divided into two types, including an N-type TFT (which uses electrons as the carriers) and a P-type TFT (which uses electric holes as the carriers).
The N-type TFT has a relatively large leakage current. To improve the reliability of the N-type TFT, the state of the art is such that a lightly doped drain (LDD) is arranged at each of two opposite sides of a channel of a semiconductor layer of the N-type TFT. The LDD is used to reduce the leakage current.
A conventional process for manufacturing an N-type TFT that involves an LDD structure comprises the following steps:
Step 1: as shown in FIG. 1, providing a substrate 100, depositing a light shielding layer on the substrate 100, and subjecting the light shielding layer to patterning to obtain a unitary light shielding bar 210.
Step 2: as shown in FIG. 2, sequentially depositing a buffer layer 200 and an amorphous silicon layer on the unitary light shielding bar 210 and the substrate 100 and subjecting the amorphous silicon layer to dehydrogenation treatment by applying an excimer laser annealing process to convert the amorphous silicon layer into a poly-silicon layer 300.
As shown in FIG. 3, the poly-silicon layer 300 obtained with Step 2 has grains of which the size is generally consistent.
Step 3: as shown in FIG. 4, coating a photoresist layer 400′ on the poly-silicon layer 300, subjecting the photoresist layer 400′ to exposure and development by applying a photolithographic process to expose two end portions of the poly-silicon layer 300, subjecting the two end portions of the poly-silicon layer 300 to N-type heavy doping by using the photoresist layer 400′ as a shielding layer, and removing the photoresist layer 400′.
Step 4: as shown in FIG. 5, depositing a gate insulation layer 400 on the poly-silicon layer 300.
Step 5: as shown in FIGS. 6 and 7, depositing and patterning a gate conductor film on the gate insulation layer 400 to obtain a gate conductor layer 500, wherein the gate conductor layer 500 has a length smaller than a length of the photoresist layer 400′ of Step 3 in order to expose parts of the un-doped portion of the poly-silicon layer 300 of Step 3, and performing one N-type light doping operation with the gate conductor layer 500 as a shielding layer so as to obtain N-type heavily doped zones 310, N-type lightly doped zones 320, and a channel zone 330.
The N-type lightly doped zones 320 constitute an LDD.
Step 6: subsequently performing a generally-used semiconductor manufacturing process, such as depositing an interlayer insulation layer and etching the interlayer insulation layer and the gate insulation layer 400 to form contact holes, depositing and etching a metal layer to form a source electrode, a drain electrode, and a gate electrode to finally form a N-type TFT having an LDD structure.
The above-described conventional process of manufacturing an N-type TFT having an LDD structure requires a photo mask to define the heavily doped zones and the lightly doped zones and needs to perform two times of ion doping. The steps of the process are numerous and the cost is relatively high. Further, since the heavily doped zones and the lightly doped zones often result in deviation in position alignment during the photolithographic operation, leading to undesired influence on the homogeneity of the TFT.
Another conventional process for manufacturing an N-type TFT having an LDD structure is using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD. This process, although saving one mask, suffers hard control of the homogeneity of the two times of etching.
FIG. 8 shows the relationship between electrical resistivity of poly-silicon having different grain sizes and doping concentration. This plot shows, under the same doping concentration, poly-silicon having different grain sizes shows different electrical resistivity. Specifically, under the same doping concentration, the smaller the grain size of poly-silicon is, the greater the electrical resistivity would be. Thus, under the same doping concentration, it is possible to achieve an effect equivalent to an LDD structure by controlling the grain size of poly-silicon.